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| SL74LS06 Hex Inverted Buffers with Open-Collector Outputs This device contains hex inverted buffers with open-collector. It performs the Boolean function Y=A in positive Logic. * High Output Voltage (30 V) * High Speed ( t PD = 8.5 ns typical) * Low Power Dissipation (PD = 18 mW per Gate) ORDERING INFORMATION SL74LS06N Plastic SL74LS06D SOIC TA = 0 to 70 C for all packages LOGIC DIAGRAM PIN ASSIGNMENT A1 1 2 Y1 A2 3 4 Y2 A3 5 6 Y3 A4 9 8 Y4 A5 11 10 Y5 FUNCTION TABLE Inputs A H Output Y L H A6 13 12 Y6 PIN 14 =VCC PIN 7 = GND L SLS System Logic Semiconductor SL74LS06 MAXIMUM RATINGS * Symbol VCC VIN VOUT Tstg * Parameter Supply Voltage Input Voltage Output Voltage Storage Temperature Range Value 7.0 5.5 30 -65 to +150 Unit V V V C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. RECOMMENDED OPERATING CONDITIONS Symbol VCC VIH VIL VOH IOL TA Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Current Ambient Temperature Range 0 Parameter Min 4.75 2.0 0.8 30 40 +70 Max 5.25 Unit V V V V mA C DC ELECTRICAL CHARACTERISTICS over full operating conditions Guaranteed Limit Symbol VIK IOH VOL Parameter Input Clamp Voltage High Level Output Current Low Level Output Voltage Test Conditions VCC = min, IIN = -18 mA VCC = min, VOH= max VCC = min, IOL = 16 mA VCC = min, IOL = 40 mA IIH High Level Input Current VCC = max, VIN = 2.7 V VCC = max, VIN = 5.5 V IIL ICC Low Level Input Current Supply Current VCC = max, VIN = 0.4 V VCC = max Total with outputs high Total with outputs low Min Max -1.5 250 0.4 0.7 20 1 -0.2 18 60 A mA mA mA Unit V A V SLS System Logic Semiconductor SL74LS06 AC ELECTRICAL CHARACTERISTICS (TA = 25C, VCC = 5.0 V, CL = 15 pF, RL = 110 , t r = 15 ns, t f = 6.0 ns) Symbol tPLH tPHL Parameter Propagation Delay, Input A to Output Y Propagation Delay, Input A to Output Y Min Max 15 20 Unit ns ns Figure 1. Switching Waveforms NOTE A. CL includes probe and jig capacitance. Figure 2. Test Circuit SLS System Logic Semiconductor |
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